The present invention pertains to bit synchronization and more particularly to a sampling phase detector.
A bit synchronizer is generally referred to as the mechanism used to reconstruct data from a noisy data stream and generate a data clock which is in phase with the noisy data stream. The data can be noise free such as from a hard-wired computer network or noisy, due to a low level RF channel.
In the case of noisy data, the data is filtered with a data filter to optimize the Signal to Noise ratio (S/N). In order to generate a reference clock, clock components are generated from the data signal and used for a phase lock loop or high Q filter input.
One method for generating the clock components from the filtered data is to take the absolute value of the derivative of the data. This operation generates a pulse every time there is a data transition. These pulses create spectral clock components at the data rate. The spectral component amplitude is directly proportional to the data transition density.
In order to generate a continuous clock, typically a phase lock loop is used to act as a narrow band filter around the spectral clock component. For a conventional phase lock loop, the phase detector gain is proportional to the data transition density. Since the phase lock loop gain is proportional to the phase detector gain, the loop gain is proportional the data transition density.
In many cases the use of a conventional phase detector is not acceptable because of the dependence of loop bandwidth on the data transition density.
What is needed is a phase detector which improves tracking performance of data bit streams for a wide range of data transition densities and utilizes simple circuitry for its implementation.